The present invention relates to pipelined analog to digital converter (hereinafter xe2x80x9cADCxe2x80x9d) systems and, more particularly, to a method and apparatus for converting element mismatch into white noise in such systems.
A conventional multi-bit per stage, pipelined ADC 10 is shown in FIG. 1. Four stages 12, 14, 16, 18 are shown; however, as shown by ellipsis 20, further stages may be included. An analog input signal VIN is provided on line 22 to stage one 12. A first residual signal VRES1 is provided on line 24 from stage one 12 to stage two 14. A second residual signal VRES2 is provided on line 26 from stage two 14 to stage three 16. A third residual signal VRES3 is provided on line 28 from stage three 16 to stage four 18. A further residual signal is provided from stage four 18 on line 30, and so forth.
Typically, all of the stages of a pipelined ADC such as ADC 10 are the same. In FIG. 1, the functional components of stage two 14 are shown by way of example. Thus, referring to the blowup 15 of stage two 14, input line 24 can be seen, which is an input to sample and hold amplifier (xe2x80x9cSHAxe2x80x9d) 32. The output of SHA 32 is provided on line 34 to an m-bit analog-to-digital subconverter (ADSC) 36, which is typically a flash ADC, and to a first input of a summing unit 38. The output of m-bit ADSC 36 is an m-bit sub-word, which is provided on line 40 both as an output to stage two 14 and is provided as an input to m-bit digital-to-analog subconverter (DASC) 42. The output of m-bit DASC 42 is provided on line 44 to a subtracting input to summing unit 38. The output of summing unit 38 is provided on line 46 to a 2m amplifier 48, which has a theoretical gain of 2m. The output of 2m amplifier 48 is provided on line 26.
In operation, stage two 14 operates as follows. An analog signal is provided on line 24 to SHA 32. SHA 32 samples the analog signal on line 24 at a succession of times and holds each such sample as a signal level on line 34 for a time sufficient to permit m-bit ADSC 36 to sense the level of the signal on line 34 and provided a digital representation thereof, as a sub-word of m-bits, on line 40. Those m-bits are converted to an analog voltage signal by m-bit DASC 42, and provided on line 44. The analog signal on line 44 is subtracted from the input signal on line 34 by summing unit 38, and the difference signal is provided on line 46 to amplifier 48, where it is amplified by a factor of 2m. The difference signal on line 46 represents the negative of the error made by the m-bit ADSC 36. Theoretically, that error signal represents the inaccuracy of the m-bit representation of the analog signal on line 24 due to the limited number of bits. That error signal, amplified by 2m, is input to the following stage of the pipeline via line 26, where a similar set of operations is performed.
After the signal propagates through n stages, a digital sample of the input signal VIN is obtained. Each of the sub-word bit lines provided at the output of the respective stage""s ADSC, e.g., bit lines 40 from ADSC 36, contributes to the overall digital word which is the digital representation provided by ADC 10 of the sampled signal VIN. The sub-word bit lines are concatenated to form this word. A new word is generated for each time period for which a sample is taken in the sample and hold amplifiers, e.g., SHA 32.
In xcexa3-xcex94 ADCs, capacitor mismatch results in DASC errors only. This DASC error can be reduced by using a number of dynamic element matching (xe2x80x9cDEMxe2x80x9d) techniques previously proposed for linearizing the DASC in multi-bit xcexa3-xcex94 ADCs. By using a time varying combination of capacitors to represent the given DASC output level, the element mismatch errors are averaged out over time, thereby linearizing the DASC. The same considerations apply to single stage digital-to-analog converters (DACs).
In a conventional pipelined ADC, there are several error sources. Two of these error sources are the DASC and the interstage gain error, both of which occur if the capacitors are not perfectly matched. Direct application of existing DEM techniques for linearizing DAC errors as used in xcexa3-xcex94 ADCs are not very effective since interstage gain errors can still degrade the overall linearity of the pipelined ADC. This can result in harmonic distortion that limits the SFDR.
One DEM technique that reduces both DASC and interstage gain error is to switch the feedback capacitors and DAC capacitors among one another. See [U. S. patent application Ser. No. 09/391,968] for a patent that uses this technique. This may be done randomly, which converts the element mismatch error into white noise. or, the switching may be done in accordance with some kind of predetermined sequence or pattern, in order to shape the resultant noise into which the mismatch error is converted. It is desired to have a high performance, low cost way of implementing such switching. Therefore, it is an object of the invention to provide high performance switching of the feedback capacitors and DAC capacitors in a DASC stage of a pipelined ADC. It is also an object of the present invention to provide such switching, while maintaining sufficient simplicity in the overall ADC design so as to permit a commercially viable product including such an ADC.
The present invention provides a method for shuffling capacitors, for application in a stage of a pipelined analog-to-digital converter that samples an input voltage at each of a sequence of sample times and provides a sequence of digital outputs representing the magnitude of the sampled input voltage. The stage includes an amplifier and a plurality of capacitors which may be connected between the input voltage and an AC ground at a first time and which may be connected between the output of the amplifier and an input of the amplifier, or which may be connected between the input of the amplifier and one of a plurality of reference voltage sources at a second time. The method includes the following steps. A plurality of coded input values are provided, each such coded value corresponding to the connection of one of the capacitors between the input of the amplifier and either the at least one voltage sources or the output of the amplifier. A predetermined sequence of control codes is provided. The coded input values are shuffled in accordance with the sequence of control codes. At the second time the plurality of capacitors are connected between the input of the amplifier and the at least one of the reference voltage sources or the output of the amplifier, in accordance with the shuffled coded input values.
These and other features of the invention will be apparent to those skilled in the art from the following detailed description of the invention, taken together with the accompanying drawings.